This invention relates to a method of fabricating high-speed bipolar transistors and highly reliable MOS field-effect transistors on the same semiconductor substrate.
Semiconductor devices fabricated in this way are generally referred to as biMOS devices. When MOS transistors of both the p-channel type (PMOS transistors) and n-channel type (NMOS transistors) are formed, the device is referred to as a biCMOS device. By combining the high-speed performance of bipolar transistors with the low power dissipation and high integration density of CMOS technology, biCMOS devices offer significant advantages in semiconductor applications such as interface logic, static random-access memory, mixed analog/digital circuits, and gate arrays.
The speed and integration level of a biMOS device can be increased by reducing the widths of the emitters of the bipolar transistors and lengths of the channels in the MOS transistors. The channel length of a MOS transistor is substantially equal to the length of its gate electrode. The attainable emitter width and gate length are determined by the smallest dimension that can be consistently resolved on the semiconductor fabrication line, which dimension is generally referred to as the design rule. Design rules in the neighborhood of one micrometer are typical at present.
The speed of a bipolar transistor is commonly measured by its cut-off frequency f.sub.T. To maximize f.sub.T it is desirable to make the emitter width equal to the design rule, or even smaller. To maximize the integration level of MOS transistors, it is similarly desirable to make the gate length equal to the design rule, but in the prior art this has proven difficult to do without adverse effects on reliability.
The problem is that as the gate length is reduced, the strength of the electric field .epsilon. in the channel tends to increase. For the standard 5-V power supply voltage, when the channel is shorter than about 1.5 .mu.m, the electric field becomes strong enough to inject so-called hot carriers into the substrate below and the gate oxide above the channel. Carriers injected into the substrate create an unwanted substrate current. Carriers injected into the gate oxide may become trapped and degrade the characteristics of the transistor. More specifically, carriers trapped in the gate oxide generate a surface potential that degrades such characteristics as the threshold voltage V.sub.T and transconductance g.sub.m, and causes increased leakage in the subthreshold region.
Another problem faced by manufacturers of biMOS semiconductor devices is the inherent complexity of the fabrication process, which raises the cost of the devices. To reduce the complexity, it is desirable to combine bipolar transistor fabrication steps with MOS transistor fabrication steps as far as possible.